TEE 206/05 Digital Electronics
Course Assessment 2 (CA2 – 25%)
Evidence of plagiarism or collusion will be taken seriously and the University regulations will be applied fully. You are advised to be familiar with the University’s definitions of plagiarism and collusion.
Instructions:
1. Answer all question.
2. The question 3 is a lab simulation of Decoder Circuits by using NI Multisim. Marks will be awarded based on the following criteria:
a) Correct results obtained from all parts practical lab work.
b) The extend of your involvement in the lab. Tutors will observe students to see if they are actively involved in the lab exercises, or do they just sit around passively and waiting for other people to do the work and copy their results.
c) Problems solving skills. Students will be observed to see if they are good at analytical thinking and problem solving when it comes to troubleshooting their circuits to make them work and to achieve the results they want.
d) How knowledgeable the students are in the subject matters. You must already possess the basic knowledge of logic circuits before you come to the lab session.
e) The overall presentation of the report, how you present your data and draw appropriate conclusions on the results obtained.
3. Remember that the plagiarism rules apply for your lab report as well. All party caught involving in plagiarism will be awarded with ZERO mark!
4. You should always ensure the working space in the lab is tidy before, during and after the lab sessions.
Question 1 (30 Marks)
A ripple counter using JK flip-flops (FF) is capable of implementing the counting sequence: F(x)={0,1,2,3,4,5} and repeats itself.
a. Draw the State Diagram for this ripple counter.
[6 marks]
b. Calculate the number of Flip-flops needed to construct this counter.
[3 marks]
c. Using the answer in (b), if the total propagation delay time for this JK FF is 10ns, calculate the allowable shortest clock pulse duration into the CLOCK of this counter for reliable operation.
[3 marks]
d. State the disadvantage of a ripple counter with multiple FFs.
[3 marks]
e. Construct the circuit of this ripple counter using JK FFs and NAND gate.
[15 marks]
Question 2 (30 marks)
a. Construct a 5-bit ring counter using rising edge triggered D Flip-flops.
[7 marks]
b. Sketch the output waveform for this ring counter for two complete cycles, given that the initial value is 00001.
[10 marks]
c. Explain the two weaknesses of a ring counter.
[2 marks]
d. The weakness of a ring counter can be solved by another type of counter called Johnson counter.
(i) Construct a 5-bit Johnson counter.
[7 marks]
(ii) State 2 advantages of Johnson counter over ring counter.
[4 marks]
Question 3 (40 marks)
Title: Simulation of Decoder Circuits by using NI Multisim
Objective: To simulate 7447 decoders to change binary input into decimal output with the seven segment display by using Multisim.
Software:
NI Multisim 14.1 and above
Procedures:
1. Open NI Multisim
2. Select 74LS47N and place it at the workspace
3. Select SEVEN_SEG_COM_A and place it at the workspace
4. Select GROUND and place it at the workspace
5. Select VCC and place it at the workspace
6. Select SPST and place it at the workspace. Repeat until 4 unit SPST appear in the workspace
7. Place 7-unit resistor 470 O and 3-unit resistor 1kO in the workspace
8. Rearrange the components as shown in Figure below:
9. Click the RUN icon to run the project.
10. Record the observation/Picture in Table 1
Result:
D C B A Observation/ Picture
0 0 0 0 1
0 0 0 1 2
0 0 1 0 3
0 0 1 1 4
0 1 0 0
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
Table 1
Note:
=0
=1
Discussion
1. What happens if the user accidentally presses the following configuration?
A=1, B=1, C=1 and D=1
2. Discuss the limitation circuit design above and method to overcome it
END OF COURSE ASSIGNMENT 2
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